Voltage sags and industrial immunity: Guide to ITIC and CBEMA curves

Introduction and Conceptual Framework of Short-Duration Transient Phenomena

In modern power systems, service continuity and power quality constitute critical pillars for the operational viability of industrial installations and data processing centers. Within the broad spectrum of conducted electromagnetic disturbances, voltage sags (dips) and brief interruptions (micro-outages) represent the most disruptive and economically damaging stochastic events. A voltage sag is formally defined, according to IEEE Std 1159 and the IEC 61000-4-30 series, as a sudden reduction in the root-mean-square (RMS) voltage below a predetermined threshold, with a duration typically ranging from half a cycle (10 ms in 50 Hz networks and 8.33 ms in 60 Hz networks) to one minute. Micro-outages, on the other hand, encompass the total loss of voltage ($V \le 10\%$ of nominal) within a similar temporal interval, requiring a rigorous analysis of the electromagnetic dynamics of connected equipment.

The proliferation of electronic loads based on high-density static power converters—such as switched-mode power supplies (SMPS), alternating and direct current variable frequency drives (VFDs), programmable logic controllers (PLCs), and computer servers—has exponentially increased the systemic vulnerability of industrial infrastructure. This equipment relies on direct rectification of the supply voltage to feed intermediate direct current (DC) buses. Consequently, any depression in the sinusoidal envelope of the supply voltage translates immediately into a voltage drop on the DC bus ($Vdc$), directly threatening the operational stability of the filter capacitors and causing nuisance tripping or catastrophic damage due to undervoltage.

From a mathematical perspective, the perturbed instantaneous voltage $v(t)$ during a three-phase or single-phase voltage sag is modeled by amplitude modulation and phase displacement induced by the grid impedance and the nature of the short circuit or switching operation that originated the disturbance:

Where $Vpeak$ is the peak value of the nominal voltage, $u(t - t_0)$ is the unit step function activated at the event start instant $t_0$, $h$ is the residual depth of the sag expressed in per unit ($pu$), $\omega$ is the fundamental angular frequency, and $\phi$ represents the initial phase angle. The severity of this phenomenon lies not solely in the magnitude of the drop ($1-h$), but in its temporal duration $\Delta t = t_f - t_0$ and in the presence of superimposed transients, such as voltage notching and high-frequency oscillations associated with the re-energization of massive inductive loads.

CBEMA and ITIC Tolerance Curves: Evolution, Thermodynamic, and Insulation Analysis

To stipulate the immunity and tolerance limits of electronic equipment against voltage variations, the defunct Computer and Business Equipment Manufacturers Association (CBEMA) developed a reference curve in the early 1980s that subsequently evolved, in the year 2000, into the ITIC (Information Technology Industry Council) standard. These curves graphically represent the tolerance threshold of the supply voltage as a function of time, delineating safe operating zones, susceptibility regions where equipment experiences unacceptable voltage drops without physical damage, and destructive overvoltage zones.

The ITIC curve is composed of several analytical regions that must be rigorously interpreted by the electrical engineer for substation design and the selection of mitigation topologies:

• Prohibited Operating Region (Upper Voltage Boundary): Sustained overvoltages or severe transients exceeding 120% of the nominal voltage. These events impose extreme dielectric stress on power semiconductor components, metal oxide varistors (MOVs), and the dielectrics of electrolytic capacitors, potentially triggering thermal runaways and insulation breakdowns.
• Continuous Operating Region (Nominal Envelope): Interval between 90% and 110% of the nominal voltage. Equipment operates within its nominal thermal and electromagnetic design parameters without degradation of service life.
• Voltage Sag Tolerance Region (Prohibited/Susceptibility Zone for Sags): Voltage drops extending from 90% down to 0% of the nominal voltage. The ITIC curve defines a stepped temporal tolerance profile: drops down to 70% of the nominal voltage must be tolerated indefinitely or for prolonged periods, whereas deeper depressions (down to 20% or 0%) are only tolerable at extremely brief intervals (ranging from 20 milliseconds down to half a cycle).
• Voltage Transients Region (Voltage Spikes): High $di/dt$ and $dv/dt$ impulses tolerated by the curve as a function of their integrated energy (typically expressed in Joules), requiring transient overvoltage surge protective device (SPD) coordination networks.

The thermodynamic and insulation analysis behind ITIC equipment tolerance is based on the energy storage capacity of the converters' DC bus. The stored energy $Edc$ in a filter capacitor bank is given by the expression:

Where $Cdc$ is the equivalent capacitance of the bus, $V_{dc,max}$ is the nominal steady-state operating voltage, and $V_{dc,min}$ is the critical threshold below which the inverter or output stage of the equipment locks out due to undervoltage (Under-Voltage Lockout - UVLO). When a voltage sag with a depth $h$ occurs, the power delivered to the load is decomposed according to the discharge dynamics of the capacitor:

If the sag duration $\Delta t$ exceeds the critical energy headroom time defined by the ITIC standard, $Vdc$ drops below $V_{dc,min}$, causing loss of synchronism in digital systems or torque collapse in frequency-inverter-driven motors.

Disturbance Parameter	Standard Limit (ITIC / IEEE Std 446)	Critical Fault Condition	Operational and Dielectric Consequence
Low Sag	90% to 70% of $V_n$ for an indefinite time.	Torque degradation in induction motors; heating due to current increase ($I^2R$).	Thermal fatigue of windings; power factor reduction due to higher inductive reactive power demand.
Medium Sag	70% to 50% of $V_n$ up to 0.5 seconds.	Undervoltage tripping in VFDs and SMPS without bus compensation.	Unscheduled stoppage of continuous processes; data loss in distributed control systems (DCS).
Severe Sag / Micro-Outage	50% to 0% of $V_n$ between 1 ms and 20 ms.	Violation of the DC bus UVLO threshold ($Vdc < V_{dc,min}$).	Instantaneous disconnection of protective relays; drop-out of electromagnetic contactors; server reboot.
Temporary Overvoltage (TOV)	110% to 120% of $V_n$ up to 1 second.	Magnetic saturation in distribution transformer cores.	Drastic increase in excitation currents and magnetization harmonics; dielectric stress in solid insulation.

Forensic Engineering Analysis of Failures Caused by Sags and Micro-Outages

The forensic study of breakdowns induced by voltage sags and micro-outages requires breaking down the transient response of critical electrical infrastructure components: power transformers, medium and low-voltage cables, switchgear, and protection systems.

Behavior of Power Transformers

During a severe voltage sag or an interruption followed by an abrupt voltage restoration (line re-closing), power transformers face severe transient inrush phenomena. If the voltage is restored at a zero-crossing of the sinusoidal wave, the magnetic flux in the transformer core can reach values that far exceed the saturation induction of the ferromagnetic material ($Bsat$). The differential equation governing the magnetic flux $\lambda(t)$ is:

With insufficient opposition from the applied voltage due to the re-closure phase shift, the magnetizing current can reach peaks of 10 to 15 times the nominal current ($I_n$). This severe electrodynamic stress causes cumulative mechanical deformations in the windings ("hoop stress" and axial forces), weakening the oil-immersed cellulosic insulation and generating micro-fissures that predispose the transformer to premature dielectric failures.

Response of Power Cables and Conductors

Although cables do not suffer direct dielectric damage from the voltage drop itself, prolonged sags that force loads to draw higher currents to maintain active power ($P = \sqrt{3} V_L I_L \cos\theta$) induce a transient increase in current density. If the protection system does not opportunely isolate the overloaded circuit, the accumulated Joule effect generates temperatures that exceed the admissible thermal limits of the insulation (for example, XLPE at 90°C in steady-state and 250°C under short circuit), accelerating the thermal aging of the polymer and reducing the dielectric strength of the cable.

Switchgear and Protection Relays

Electromagnetic contactors and auxiliary control relays are highly sensitive to micro-outages. The electromagnetic force $Fem$ developed by a contactor coil is proportional to the square of the supply voltage:

When the voltage drops below 65%-70% of the nominal voltage for an interval exceeding the mechanical retention time (typically 10 to 20 ms), the antagonistic spring force overcomes the electromagnetic force, causing the inadvertent opening of the main contacts. This generates severe electrical arcs at the contacts, contact welding (chattering), and the cascading interruption of critical industrial processes. Likewise, microprocessors in modern numerical protective relays require redundant power supplies and internal capacitive energy storage systems (capacitive ride-through) to prevent firmware resetting during deep sags, which would leave the grid without active selective protection.

Advanced Industrial Design and Mitigation Strategies

Mitigating the adverse effects of voltage sags and micro-outages requires a holistic approach combining component oversizing, rigorous selection of active and passive compensation topologies, and parametric coordination based on international standards.

Dynamic Voltage Restorers (DVR)

The Dynamic Voltage Restorer (DVR) is positioned as the most efficient and rapid solid-state solution for protection against sags and micro-outages in sensitive industrial buses. The DVR is a static converter connected in series with the grid via a coupling transformer. Its operational principle consists of injecting a three-phase compensating voltage $vinj(t)$ in phase with the grid voltage to restore the perfect sinusoidal profile at the protected load:

The apparent power required by the DVR during a sag of depth $h$ and load current $Iload$ is calculated using the following analytical relation:

The design of the DVR's energy storage system (ultracapacitor banks or high-discharge-density batteries) must be sized to sustain power injection for the maximum estimated duration of the voltage sag (typically up to 3 to 5 seconds for severe events).

High-Efficiency Uninterruptible Power Supply (UPS) Systems

For ultra-sensitive IT and control loads, double-conversion online UPS systems (VFI - Voltage and Frequency Independent according to IEC 62040-3) guarantee total galvanic isolation and strict voltage regulation. However, their integration requires evaluating thermal performance and parasitic losses in inverter semiconductors. The efficiency factor $\eta$ of a VFI topology is optimized through the implementation of space vector pulse width modulation (SVPWM) and the use of silicon carbide devices (SiC-MOSFETs), which drastically reduce switching losses at frequencies above 20 kHz.

Practical Application and Engineering Analysis via Vexten Suite

To illustrate the rigorous application of the theoretical concepts presented, an industrial case study evaluated under the computational guidelines of the Vexten Suite platform is developed below. This integrates short-circuit calculation according to IEC 60909 / IEEE 141, cable sizing with harmonic correction factors according to IEC 60287 / NEC 310, and resonance mitigation.

Reference Industrial Electrical System Parameters

• Medium Voltage Nominal Supply Voltage: $U_n = 23.0 \, kV$ (Three-phase, 50 Hz).
• Grid Short-Circuit Power (Transmission Substation): $Ssc3 = 500 \, MVA$.
• Main Step-Down Transformer: $Str = 10 \, MVA$, Ratio $23 \, kV / 0.69 \, kV$, Short-Circuit Voltage $uk = 6.5\%$, Copper Losses $Pcu = 45 \, kW$.
• Aggregated Low-Voltage Critical Load (Main 690 V Bus): $Sload = 7.5 \, MVA$, Power Factor $\cos\theta = 0.85$ lagging, with orders 5 and 7 harmonic presence representing a total current harmonic distortion ($THD_i$) of 22%.

Step 1: Short-Circuit Calculation and Voltage Sag Depth Evaluation (IEC 60909)

The occurrence of a three-phase short circuit on a remote secondary bus connected via an interconnection cable is evaluated. The equivalent system impedance at the medium voltage level is determined as:

Where $c$ is the voltage factor for calculating maximum short-circuit currents (1.1 for medium voltage networks). The equivalent impedance referred to the transformer secondary (690 V) is calculated by incorporating the transformer impedance $Ztr$:

When a short circuit occurs on an adjacent feeder, the instantaneous voltage drop experienced by the critical 690 V bus bar is calculated using the voltage divider formed by the source impedance and the fault line impedance. If the fault short-circuit impedance generates a drop that depresses the voltage to $45\%$ of nominal ($\Delta t = 120 \, ms$), direct verification with the ITIC curve demonstrates that the event lies heavily within the prohibited zone, unequivocally requiring the installation of a solid-state DVR or DC bus storage system.

Step 2: Cable Sizing and Harmonic Derating (IEC 60287 / NEC 310)

Due to the high harmonic content ($THD_i = 22\%$), zero-sequence currents and higher-order currents increase skin effect and proximity effect losses in copper conductors. Low-voltage cable sizing is performed by applying ambient temperature ($F_t$), grouping ($F_g$), and harmonic ($Fharm$) correction factors stipulated in the IEC 60287 standard. The corrected design current $Iz$ is expressed as:

For a fundamental load current of $Iload = 6,275 \, A$ (calculated from $Sload = 7.5 \, MVA$ and $U = 690 \, V$), and adopting a harmonic correction factor $Fharm = 0.82$ due to current concentration in the neutral and phase conductors caused by triplen and characteristic harmonics (5th and 7th), the corrected design current rises to:

Vexten Suite selects a parallel array of multiple large-cross-section single-core XLPE-insulated cables, optimizing the geometric layout in cable trays to minimize mutual impedance and avoid localized hot spots that exacerbate the risk of dielectric failure under thermal overload transients.

Step 3: Resonance Mitigation and Power Factor Correction

The presence of capacitor banks for power factor correction in the presence of non-linear loads can give rise to parallel or series harmonic resonance phenomena. The parallel resonance frequency $f_p$ between the compensation capacitors $C$ and the transformer short-circuit inductance $Ltr$ is determined by:

If $f_p$ coincides with a characteristic harmonic (such as the 5th order, i.e., 250 Hz in 50 Hz networks), catastrophic amplification of voltage and harmonic currents occurs, generating spurious protection trips and thermal cracking of capacitor dielectrics. To neutralize this risk, Vexten Suite implements the design of detuned reactors typically tuned to $7\%$ or $14\%$ of the capacitive reactance, shifting the resonance frequency below the lowest dominant harmonic ($f_p < 4.7 th$ order), thus guaranteeing robust stability against voltage sags and combined harmonic distortion.

Vexten Suite Parameter	Base Design Value	Applied Normative Criterion	Analytical Verification Result
Short-Circuit Current (3ɸ)	41.8 kA (Initial symmetrical)	IEC 60909 / IEEE 141	Electrodynamic and thermal withstand met in 50 kA switchgear.
Voltage Sag Depth	45% of $V_n$ (120 ms duration)	ITIC Curve / SEMI F47	Outside safe tolerance zone; requires solid-state DVR.
Cable Derating Factor	$Fharm = 0.82$ ($THD_i = 22\%$)	IEC 60287 / NEC 310	Parallel arrangement of XLPE conductors optimized to prevent critical thermal spots.
Parallel Resonance Frequency	Shifted to 185 Hz (with 7% reactor)	IEEE Std 519	Effective elimination of 5th and 7th harmonic amplification.

Conclusions and Definitive Criteria for the Design Engineer

The comprehensive analysis of voltage sags and micro-outages transcends the simple selection of overcurrent protections; it demands a deep understanding of the electromagnetic interaction between the distribution network and industrial power electronics. ITIC and CBEMA curves constitute fundamental tools, but they must be complemented with power quality audits based on harmonic measurements and advanced transient simulations. The rigorous implementation of international standards (IEC 61000, IEC 60909, IEC 60287, IEEE 141) alongside high-level engineering calculation tools such as Vexten Suite ensures the design of resilient electrical infrastructures capable of safeguarding operational continuity and mitigating economic losses derived from modern industrial vulnerability.